Improving On-state current and Ambipolarity of TFET using Gate-Drain and Gate Dielectric Engineering

Authors

  • Gaurav Saini NIT Kurukshera, Haryana
  • Avinash Ganta School of VLSI Design and Embedded Systems, NIT Kurukshetra, Haryana, India

DOI:

https://doi.org/10.56042/ijpap.v62i7.7715

Keywords:

Ambipolarity, Gate overlapping, TFET, Tunnelling barrier width

Abstract

This article presents the Gate Overlap on Drain with Hetero Gate Dielectric TFET (GDHD-TFET), a novel tunnel FET structure aimed at addressing the low ON current and ambipolar leakage observed in traditional TFETs. By investigating the combined effects of hetero gate dielectric and gate-drain overlapping, the GDHD-TFET offers a significant improvement in design compared with conventional TFET design. Unlike traditional approaches that focus solely on regulating the tunnel barrier widths at the channel-source junction, the GDHD-TFET simultaneously improves the tunnel barrier widths at both channel-source and channel-drain junctions. As a result, the GDHD-TFET achieves remarkable improvements in ON current and ambipolar conduction, surpassing traditional TFET performance by factors of 102 and 104, respectively. Furthermore, it maintains low subthreshold swing (SS) of 29.3 mV/dec indicating its potential for low-power applications.

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Published

2024-06-27

How to Cite

Improving On-state current and Ambipolarity of TFET using Gate-Drain and Gate Dielectric Engineering. (2024). Indian Journal of Pure & Applied Physics (IJPAP), 62(7), 607-613. https://doi.org/10.56042/ijpap.v62i7.7715

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