Numerical Simulation and Optimization of a Novel Dopingless Vertical Nanowire TFET for Low Power Memory Applications

Abstract

The use of portable devices has significantly increased in today’s life, due to this the performance parameters of low power application devices are the key feature to notice. Dopingless devices are the new attracting techniques for low power applications and high ION / IOFF factor. The nanowire devices utilize the gate control over the channel to reduce OFF current  in the device and vertical structure of device helps to enhance the tunnelling mechanism in tunnel FETs. In this work a dopingless vertical nanowire tunnel FET is designed and simulated. The simulation results are showing charge plasma dopingless VNWTFET in both P-type and N-type, performance characteristics like drain current (ID), transconductance (gm), gate to drain capacitance (CGD), gate to source capacitance (CGS), total gate capacitance (CGG), cut off frequency (fT), energy, potential, electron and hole concentration, electric field, electron band to band tunnelling. Then the 6T CP-VNWTFET based SRAM circuit is demonstrated. The analysis of circuit shows that circuit of SRAM designed by 6T CP-VNWTFET gives preferably superior signal to noise margin like RSNM of 376.43mV and WSNM of 433.35mV at VDD = 1.0V; also, a reduced read delay as 4.1ns and write delay as 0.18ns when compared with conventional 6T TFET and 7T TFET device-based SRAMs. The leakage power of proposed device-based SRAM circuit is also showing better performance at all the voltage range.