A New Threshold Voltage Model of Short Channel FD-SOI MOSFET by Green’s Function Approach to Analytically Solving 2-D Laplace/Poisson’s Equations in Multi-Zone Structure and Applying it to Study Post-Implant Annealing Effect

Abstract

This paper reports on new analytical models of front and back gate threshold voltages for short-channel fully depleted silicon-on-insulator (FD-SOI) MOSFETs, considering an annealed non-uniform impurity profile resulting from retrograde doping required for vertical channel engineering. For this purpose, the exact solutions of multi-zone 2-D Laplace/Poisson equations have been obtained by adopting a new Green’s function approach. Since the SOI MOSFET is a three-layer structure, we have established new multi-zone Green’s functions that incorporate the combined effects of all three layers joined together at the interfaces. This approach allows for a more nuanced analysis of potential distributions in the three-layer structure of SOI devices, taking into account the interactions between the different layers within the device. Considering the explicit potential relations thus derived, we formulate closed-form expressions of front and back gate threshold voltages, which include the front and back gate charge coupling effects, the profile annealing effect, and the effects of drain and gate voltages. This holistic perspective is crucial because it enables a more accurate understanding of how these variables interact and affect device operation, thereby enhancing the predictive capability of the models. In addition to the front and back gate threshold voltages, their biasing counterparts—the respective back and front gate voltages—have also been formulated, accounting for the aforementioned effects, in order to determine operational modes of the device under study. Finally, the results obtained from the new model have been rigorously validated by comparison with data generated by ATLAS software, revealing excellent alignment between the two. This validation not only supports the reliability of the proposed models but also enhances their applicability in practical semiconductor device simulation and design.