Reversed C-shape Pocket Double Gate TFET with dual-κ Spacers

Abstract

The study delves into the evaluation of the Double Gate Tunnel Field-effect Transistors (DGTFET) structures, Reversed C-shape Pocket TFET (RCSP-TFET), and RCSP-TFET with dual-k spacers. The TFET supports current generation through band-to-band tunneling among source/drain and channel regions. By strategically placing the three n+ pockets nearby the source-channel region, the tunneling barrier width is lowered and the current is increased in the ON-state. Subsequent to the calibration of the DGTFET utilizing diverse tunneling models, a comprehensive evaluation of the performance of the RCSP-TFET is undertaken. This assessment is executed through the meticulous optimization of the thickness and length of the n+ pocket, thereby ensuring precise and dependable outcomes. Furthermore, the spacer walls comprised of an amalgamation of high-k and low-k dielectrics is intended to augment the performance of the device. This approach seeks to optimize efficacy and improve operational capabilities. The optimized structure reveals a higher ON-state current (I_ON)= 7.0 x 10^-5 (A/µm), the ON-OFF current ratio (I_ON/I_OFF) , Ambipolar Current (I_Amb)= 2.1x 10^-13 (A/µm), reduced subthreshold swing (SS)=11.09 mV/decade) in the RCSP-TFET structure with dual-k spacers. The results imply the potential feasibility of the RCSP-TFET with dual-k spacers as a compelling choice for next-generation semiconductor technology.