Active Inductor-based Multistage DCO Design for Low Power VLSI Applications

Authors

  • Manju Department of Electrical and Electronics Engineering, Guru Jambheshwar University of Science and Technology, Hisar 125 001, India
  • Ramnish kumar Department of Electrical and Electronics Engineering, Guru Jambheshwar University of Science and Technology, Hisar 125 001, India
  • Manoj kumar Department of Electronics and Communication Engineering, National Institute of Technology, Delhi 110 036, India

DOI:

https://doi.org/10.56042/ijpap.v64i9.31377

Keywords:

DCO, Active inductor, CMOS-Inverter, Delay stage, MOS varactor, NAND gate

Abstract

This paper investigates simulation-based analysis of 3-stage, 5-stage, and 7-stage digitally controlled oscillator (DCO) architectures implemented in 90 nm CMOS technology using the Cadence Virtuoso tool at a supply voltage of 1 V. The proposed DCO architectures are realised by cascading alternate delay stages in a closed-loop configuration to form a ring oscillator, where the output is fed back to the input to sustain oscillation. The delay stages comprise a CMOS inverter and a NAND gate–based inverter delay stage, combined with a PMOS switching network, MOS varactors and active inductors to achieve wide frequency tuning, high resolution, and low power operation. The results are analysed with varying control bits from 000 to 110 and voltage from 0.5 V to 1.0 V at different transistor widths (W = 1 µm, 1.5 µm, and 2 µm). For the  3-stage DCO, the oscillation frequency varies from 4.018 GHz to 0.517 GHz at W = 1 µm, 2.945 GHz to 1.822 GHz at  W = 1.5 µm, and 2.309 GHz to 1.557 GHz at W = 2 µm, as the digital control bits are swept from 000 to 110, while power consumption decreases from 451.8 mW to 404.7 mW. Similarly, the 5-stage DCO exhibits a frequency tuning range of 1.832 GHz to 1.120 GHz at W = 1 µm, 1.405 GHz to 0.825 GHz at W = 1.5 µm, and 1.110 GHz to 0.655 GHz at W = 2 µm, while power consumption ranges from 451.6 mW to 404.3 mW. For the 7-stage DCO, the frequency tuning range is  1.188 GHz to 0.761 GHz at W = 1 µm, 0.873 GHz to 0.564 GHz at W = 1.5 µm, and 0.693 GHz to 0.448 GHz at W = 2 µm, with power consumption again decreasing from 451.6 mW to 404.3 mW. Similarly, the performance of the proposed DCO architectures is evaluated over a supply voltage range from 0.5 V to 1.0 V. The results determine that the DCO attains a wide frequency tuning range, high tuning resolution, and low power consumption through the combined operation of digitally controlled PMOS switching networks, voltage-controlled MOS varactors, and active inductors. 

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Published

2026-09-10

How to Cite

Active Inductor-based Multistage DCO Design for Low Power VLSI Applications. (2026). Indian Journal of Pure & Applied Physics (IJPAP), 64(9). https://doi.org/10.56042/ijpap.v64i9.31377

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