Design and Analysis of Three-Stage and Five-Stage Digitally Controlled Oscillators with Low-Power Consumption

Abstract

This paper presents a design and performance analysis of 3-stage and 5-stage Digitally Controlled Oscillators (DCOs), incorporating NAND gate-based inverter and transmission gate-based pseudo-inverter delay stages. The circuits are designed using 90 nm CMOS technology and simulated with the Cadence Virtuoso tool at a supply voltage (VDD) of 0.7 V. To enhance frequency tuning and minimize power consumption, the proposed architectures utilize a PMOS switching network in conjunction with MOS varactors. When the PMOS switching network control bits are varied from 000 to 110, the 3-stage DCO exhibits a power consumption range from 314.5mW to 323.4mW and a corresponding frequency variation between 4.829 GHz to 3.552 GHz. Under similar conditions, the 5-stage DCO demonstrates power consumption between 314.2 mW to 323.6 mW, with frequency 2.887 GHz to 1.645 GHz. Furthermore, when configured using MOS varactor control bits ranging from 000 to 110, the 3-stage DCO exhibits a power consumption of 314.5 mW and frequencies from 4.829 GHz to 4.458 GHz, while the 5-stage DCO operates at 314.2 mW in power with frequencies ranging from 2.887 GHz to 2.623 GHz. This work also presents the variation in power consumption and oscillation frequency as the supply voltage is
swept from 0.4 V to 0.9 V.