Impact of Source Contact Engineering on Memory Window Enhancement in PVDF/ZnO Ferroelectric Thin-Film Transistors

Abstract

In this work, memory window (MW) modulation in bottom gate ZnO/PVDF ferroelectric thin-film transistors (FeTFTs) is studied using Schottky and Ohmic source/drain contact configurations using a TCAD simulation framework. The influence of contact dependent carrier injection and ZnO background electron concentration ranging from 10¹⁵ to 10¹⁷ cm⁻³ on polarization screening and hysteresis properties is comprehensively examined under a transient gate dual sweep voltage of 0 to 20 V with a total pulse duration of 2 μs. Devices with Schottky contacts show clearly defined hysteresis loops in input characteristics with MW within 2.86 and 3.69 V, whereas devices with Ohmic contacts indicate significantly lower MW between 0.21 and 0.22 V, which is attributed to increased electrostatic charge screening and unrestricted carrier supply. Further the observed behavior is analyzed using carrier concentration distribution analysis plots which shows that reduced carrier concentration at the Schottky interface enhances polarization induced potential modulation, while higher carrier availability in Ohmic devices lowers this effect. In ZnO/PVDF FeTFT platforms, this work clearly shows that source/drain contact engineering is a governing mechanism for controlling polarization charge screening and improving ferroelectric memory performance.