Enhanced RF Performance Using Trench-Based Junctionless FET: Design and Analytical Study

Abstract

To enhance the analog/RF performance, a dual-channel trench based junctionless FET (JLT) is being proposed. The planned structure's gate is set in a vertical trench, with two channels cut out on either side of it. HJLT and MJLT, the heavily and moderate doped drain concentrations for the suggested device, are explored correspondingly. The devices' performance parameters are assessed and contrasted with respect to drain current (I_D), unity-gain cut-off frequency (f_t), transconductance (g_m), and maximal oscillation frequency (f_max) in a TCAD tool (ATLAS) through 2D numerical simulations. As a result, the suggested topology makes sense for analog and radio frequency applications. At 20 nm gate length, the proposed HJLT is shown to provide f_max, f_T, and peak g_m of, 2300 GHz, 580 GHz, and 2710 μS/μm respectively. As a result, the suggested topology makes sense for analog and radio frequency applications.