Highly-Stable and Lower-Power Static Random-Access Memory Design in Carbon Nanotube Field Effect Transistor Nanotechnology

Authors

  • Ekta Jolly School of Electronics & Communication Engineering, Shri Mata Vaishno Devi University, Katra 182 320, India
  • Vijay Kumar Sharma Department of Electronics & Communication Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur 273 010, India
  • Anil Kumar Bhardwaj School of Electronics & Communication Engineering, Shri Mata Vaishno Devi University, Katra 182 320, India

DOI:

https://doi.org/10.56042/ijpap.v63i12.21046

Keywords:

CNTFET, LMT-SRAM, SNM, Stability, Energy-efficient, N-curve, PVT, K-S Test

Abstract

Carbon nanotube field-effect transistor (CNTFET) technology is emerging as a potential replacement for metal oxide semiconductor field-effect transistor (MOSFET) technology. CNTFET uses carbon nanotubes (CNTs) as a channel, due to which CNTFET technology displays superior electrical characteristics, like increased carrier mobility, ballistic carrier transport, and adjustable threshold voltage. While working with MOSFETs, different short-channel effects (SCEs) result in the degradation of various performance parameters. The MOSFET-based static random-access memory (SRAM) faces various SCEs, leakage, and higher power consumption at smaller technology nodes. Therefore, this research work proposes a CNTFET-based SRAM cell design that utilizes a reliable leakage minimization technique (LMT) to overcome these challenges. The proposed LMT-SRAM circuit is designed for low-power, high-performance embedded memory. To design the LMT-SRAM cell, a reliable leakage minimization block is inserted between the pull-up and pull-down networks of the cross-coupled inverters, which reduces the power dissipation. CNTFETs, because of their superior electrical properties, help the proposed design to achieve improved performance metrics. The proposed LMT-SRAM circuit is simulated with the Stanford University 32nm CNTFET technology model using HSPICE for a power supply of 0.9V and at room temperature conditions. The simulation results justify that the proposed CNTFET-based LMT-SRAM cell attains 98.6% reductions in average power dissipation when compared to previous designs. The proposed design shows 91.6% faster execution while in write mode and 33.6% faster execution while in read mode. The design has also shown remarkable stability and variability during read and write operations. The butterfly and N-curve methods are used to determine static noise margin (SNM) for the proposed LMT-SRAM cell. Monte Carlo (MC) simulations are performed to verify SNM stability across process, voltage, and temperature (PVT) variations. The Kolmogorov-Smirnov (K-S) test is also performed using MATLAB to determine the normality of the dataset obtained from the MC sample run.

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Published

2025-12-17

How to Cite

Highly-Stable and Lower-Power Static Random-Access Memory Design in Carbon Nanotube Field Effect Transistor Nanotechnology. (2025). Indian Journal of Pure & Applied Physics (IJPAP), 63(12). https://doi.org/10.56042/ijpap.v63i12.21046

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