Design and characteristics exploration of an InAs-source-based electrostatic doped vertical nanowire TFET
DOI:
https://doi.org/10.56042/ijems.v33i03.23089Keywords:
Dopingless transistor, Indium Arsenide source, InAs/Si interface, Nanowire transistor, Silvaco TCAD, VNW-TFETAbstract
In this manuscript, the nanotube structure with vertical architecture and indium arsenide-based source has been proposed. In the proposed device, the electrostatic doping (ED) has been applied to eliminate the doping ambiguities like expensive thermal budget (ETB) and random dopant fluctuation (RDF). RF and analogue metrics, including transconductance (gm), transfer characteristics (ID–VGS), output conductance (gd), output characteristics (ID–VDS), cut-off frequency (fT), and gate capacitance (CGG), have been utilized to observe the device characteristics. The structural parameters of the device like energy band, potential, electric field, and carrier concentration are also investigated. The InAs-based source electrostatic doped VNW-TFET (InAs-S-ED-VNW-TFET) has shown better performance as compared to the conventional or Si-based source VNW-TFET (Si-S-ED-VNW-TFET) due to its higher mobility, lower bandgap, and lower effective mass, resulting in a higher tunneling rate. With the inclusion of electrostatic doping, uniform doping has been achieved throughout the device. The device has been optimized by achieving a steeper subthreshold slope of 19.8mV/Dec, higher ON current 8.99µA/µm and higher ON/OFF current ratio 1.23X1013.