Design and characterization of a low-leakage, high-stability SRAM cell for IoT applications

LOW-LEAKAGE, HIGH-STABILITY SRAM FOR IOT APPLICATIONS

Abstract

The typical memory for very large-scale integrated (VLSI) circuits has traditionally been static random-access memory (SRAM) because it has offered faster speeds compared to other alternatives. However, SRAM has been associated with a high-power consumption rate. Researchers have recognized the importance of lowering the power consumption of SRAM cells due to their critical role in memory architecture. This literature review has aimed to provide innovative and effective strategies for designing low-power SRAM cells. Several circuit topologies and methodologies have been introduced to compute stability, leakage current, delay, and power, and novel techniques for designing SRAM cells based on eight transistors (8T) have been proposed. SRAM has frequently been chosen over dynamic random-access memory (DRAM) because it has demonstrated faster speeds and lower power consumption. It has been named "static" because no modification or action, such as refreshing, has been required to maintain data intact. However, leakage current in SRAM has often increased and impaired its performance as technology nodes have been scaled down. Voltage scaling has been adopted as a solution to this issue, although it has also affected the stability and latency of SRAM. A separate (isolated) read port has been employed to
enhance read stability, while a negative bit-line (NBL) write-aid circuit has been implemented to improve write capability. The suggested design has been compared to state-of-the-art work in terms of write static noise margin (WSNM), write latency, read static noise margin (RSNM), and other metrics. Future research has been directed toward exploring novel circuit topologies and methodologies to further enhance stability, reduce leakage current, and minimizes delay and power consumption. Researchers have also investigated the performance of SRAM cells at smaller technology nodes to develop new techniques for maintaining stability and  performance at these scales. Additional efforts have been made to explore new approaches to voltage scaling and to develop methods that improve the read and write capabilities of SRAM cells.